![]() ![]() In hardware design, formal property verification is used throughout the design cycle. In a formal verification approach, a single symbolic simulation run provides full coverage of the input space and thus exhaustively verifies the program. The main deficiency of formal verification is its limited capacity compared with simulation. Both hardware and software designs are experiencing a verification crisis since simulation-based logic verification is becoming less and less effective due to the growing complexity of the systems. It offers an exhaustive verification technology, which is orders of magnitude more efficient than scalar exhaustive simulation. ![]() Formal property verification enjoys major advantages over simulation.
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